This invention relates to the field of solid state electronics, and particularly to a process for making heterojunction bipolar transistors using a dual lift-off technique to provide self alignment of the emitter and base contacts.
In heterojunction bipolar transistors (HBTs), the intrinsic transistor speed is governed by the vertical layer structure of the device which is incorporated during growth of the wafer. This aspect of the device can be optimized and controlled using molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) growth technology.
Subsequent processing of the wafer determines the lateral extent of the different device regions (emitter area, extrinsic base area, and collector area). Obtaining accurate lateral geometry is important because it determines the magnitude of parasitic extrinsic circuit elements associated with the transistor, notably, base-collector capacitance and base resistance. Currently, these parasitic elements have a major role in determining bipolar circuit speed, particularly in HBTs which are intrinsically extremely fast.
The dimensions of the transistor also influence the power dissipation at which the highest speeds are achieved. It is important to reduce the dimension of HBTs in order to both decrease their parasitic elements and to improve their speed-power performance. This requires processing techniques which can accurately produce very small geometry HBTs.
In typical processes, minimum device dimensions are determined by three factors: (1) Minimum lithographic feature size, (2) Variations of dimensions as a result of process nonuniformity, and (3) alignment inaccuracies. Currently, features as small as 0.8 to 1 .mu.m can be defined using optical lithography, and dimensions can be reasonably reproduced with available process controls. However, the third factor, alignment inaccuracies, is a considerable problem in fabricating HBTs. To prevent two separate neighboring mask layers from overlapping, it is necessary to provide a substantial tolerance in the geometry of the transistor. However, if the same mask can be used to define neighboring regions (called self-alignment), the tolerance can be reduced to zero and the size of the HBT reduced.
In an HBT structure, there are three patterns that must be critically aligned to one another (corresponding to two critical alignments). These are: (1) the active emitter area, (2) the emitter contact, and (3) the base contact. There are prior art HBT processes which utilize some self-alignment to eliminate one registration or, at least, render it non-critical. For example in the process described by Nagata, et al, the base and the base contact are produced without requiring separate masks by depsiting an SiO.sub.2 sidewall to separate the emitter and the base contact (`A new self-aligned structure AlGaAs/GaAs HBT for high speed digital ciruits`, Inst. Phys. Conf. Ser. 79, 1985, pp. 589-594). However, further improvement is desirable to provide a fully self-aligned process in which the critical dimensions of all three patterns are defined (or made non-critical) with a single photoresist mask step.